1. Field of the Invention
The present invention relates generally to methods for fabricating field effect transistor (FET) devices within microelectronic fabrications. More particularly, the present invention relates to method for fabricating, with enhanced performance, field effect transistor (FET) devices within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
Indigenous within the fabrication of microelectronic fabrications, and particularly within the fabrication of semiconductor integrated circuit microelectronic fabrications, is the fabrication of field effect transistor (FET) devices within microelectronic fabrications, and in particular within semiconductor integrated circuit microelectronic fabrications.
Field effect transistor (FET) devices are desirable and indigenous within the art of microelectronic fabrication insofar as field effect transistor (FET) transistor devices are generally readily fabricated while employing in part self aligned methods which are in turn readily scalable when fabricating field effect transistor (FET) devices within microelectronic fabrications.
While field effect transistor (FET) devices are thus particularly desirable in the art of microelectronic fabrication and often essential in the art of microelectronic fabrication, field effect transistor (FET) devices are nonetheless not entirely without problems in the art of microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic fabrication.
In that regard, as microelectronic fabrication integration levels have increased and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly difficult within the art of microelectronic fabrication to fabricate within microelectronic fabrications microelectronic devices, and in particular field effect transistor (FET) devices, with enhanced structural integrity, and thus enhanced performance.
It is thus desirable in the art of microelectronic fabrication to fabricate within microelectronic fabrications field effect transistor (FET) devices with enhanced structural integrity, and thus enhanced performance.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed within the art of microelectronic fabrication, and in particular within the art of semiconductor integrated circuit microelectronic fabrication, for fabricating microelectronic devices, and in particular field effect transistor (FET) devices, with desirable properties in the art of microelectronic fabrication.
Included among the methods, but not limiting among the methods, are methods disclosed by: (1) Lee et al., in U.S. Pat. No. 5,468,665 (a method for forming within a field effect transistor (FET) device a lightly doped drain (LDD) low dose ion implant region adjacent a gate electrode within the field effect transistor (FET) device absent use of a spacer layer adjoining the gate electrode as a lightly doped drain (LDD) low dose ion implant mask, by instead employing a two step patterning method and two step ion implant method such that a source/drain region adjacent the gate electrode is formed prior to the lightly doped drain (LDD) low dose ion implant region adjacent the gate electrode); (2) Juengling, in U.S. Pat. No. 6,087,239 (a method for forming a field effect transistor (FET) device while employing as an ion implantation mask formed adjoining a gate electrode a sacrificial spacer layer formed of a readily etchable silicon-germanium alloy material); (3) Gardner et al., in U.S. Pat. No. 6,127,234 (another method for forming a field effect transistor (FET) device while employing as an ion implantation mask formed adjoining a gate electrode a sacrificial spacer layer formed of a readily etchable silicon-germanium alloy material); and (4) Ling et al., in U.S. Pat. No. 6,153,455 (a method for forming a field effect transistor (FET) device while employing as an ion implantation mask formed adjacent a gate electrode a sacrificial spacer layer formed of a silicon nitride material).
Desirable in the art of microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic fabrication, are additional methods and materials which may be employed for forming, with enhanced structural integrity, field effect transistor (FET) devices within microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a method for forming within a microelectronic fabrication a field effect transistor (FET) device.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the field effect transistor (FET) device is fabricated with enhanced structural integrity.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for fabricating a field effect transistor (FET) device.
To practice the method of the present invention, there is first provided a semiconductor substrate. There is then formed over the semiconductor substrate a blanket gate electrode material layer. There is then formed over the blanket gate electrode material layer a patterned auxiliary layer. There is then formed adjacent a sidewall of the patterned auxiliary layer and also over the blanket gate electrode material layer a sacrificial spacer layer. There is then etched, while employing at least the patterned auxiliary layer and the sacrificial spacer layer as a mask, the blanket gate electrode material layer to form a once patterned gate electrode material layer. There is then implanted, while employing at least the once patterned gate electrode material layer as a mask, a source/drain region within the semiconductor substrate. There is also stripped from adjacent the sidewall of the patterned auxiliary layer the sacrificial spacer layer. There is then etched, while employing the patterned auxiliary layer but not the sacrificial spacer layer as a mask, the once patterned gate electrode material layer to form a gate electrode. There is then formed adjacent a sidewall of the gate electrode a permanent spacer layer. Finally, there is then implanted, while employing at least the gate electrode and the permanent spacer layer as a mask, at least one additional ion implant structure within the semiconductor substrate.
There is provided by the present invention a method for fabricating within a microelectronic fabrication a field effect transistor (FET) device, wherein the field effect transistor (FET) device is fabricated with enhanced structural integrity.
The present invention realizes the foregoing object by employing when fabricating the field effect transistor (FET) device in accord with the present invention a two step etching method for forming from a blanket gate electrode material layer a gate electrode employed within the field effect transistor (FET) device. By employing the two step etching method for forming from the blanket gate electrode material layer the gate electrode employed within the field effect transistor (FET) device, a source/drain region within the field effect transistor (FET) device may be formed prior to forming an additional ion implant structure within the field effect transistor (FET) device (such as but not limited to an additional lightly doped drain (LDD) low dose ion implant structure within the field effect transistor (FET) device or an additional pocket ion implant structure within the field effect transistor (FET) device), such that the additional ion implant structure which is formed within the field effect transistor (FET) device while employing the gate electrode and a permanent spacer formed adjacent thereto as an ion implant mask need not be exposed to a thermal annealing processing employed for thermal annealing processing of the source/drain region within the field effect transistor (FET) device. Thus, the structural integrity of the additional ion implant structure employed within the field effect transistor is enhanced, and consequently also the performance of the field effect transistor (FET) device is enhanced.
The method of the present invention is readily commercially implemented.
The present invention employs methods and materials as are generally known in the art of microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic fabrication, but employed within the context of a specific ordering and specific process limitations to provide the present invention. Since it is thus a specific ordering and specific process limitations which provide at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.